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Modern SIMD Vectorization in C++: From Auto-Vectorization to AVX2 Intrinsics

PerformanceC++

Standard scalar processor instructions process one piece of data at a time (Single Instruction, Single Data - SISD). When crunching floating-point mathematics, audio signals, or matrix multiplications, modern x86 and ARM processors provide vector execution units capable of processing 4, 8, or 16 numbers in a single clock cycle through SIMD (Single Instruction, Multiple Data).

Here is a guide to hardware vectorization in modern C++, demonstrating when the compiler can auto-vectorize and how to write hand-crafted AVX2 intrinsics.

What is SIMD?

CPU registers usually hold 64 bits (like rax or rbx). SIMD extensions introduce significantly wider vector registers:

  • SSE: 128-bit registers (xmm0-xmm15) $\to$ 4 floats or 2 doubles
  • AVX / AVX2: 256-bit registers (ymm0-ymm15) $\to$ 8 floats or 4 doubles
  • AVX-512: 512-bit registers (zmm0-zmm31) $\to$ 16 floats or 8 doubles
Scalar Addition:
[ a0 ] + [ b0 ] = [ c0 ]  (1 operation per cycle)

AVX2 SIMD Addition (_mm256_add_ps):
[ a7 | a6 | a5 | a4 | a3 | a2 | a1 | a0 ]
                   +
[ b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 ]
                   =
[ c7 | c6 | c5 | c4 | c3 | c2 | c1 | c0 ]  (8 floats simultaneously)

Level 1: Guiding Compiler Auto-Vectorization

Modern optimizing compilers (GCC with -O3 -march=native or Clang) will automatically vectorize loops if certain conditions are met.

Consider a naive array multiplication:

void multiply_arrays(float* a, float* b, float* c, size_t n) {
    for (size_t i = 0; i < n; ++i) {
        c[i] = a[i] * b[i];
    }
}

Often, the compiler cannot safely vectorize this loop because of pointer aliasing: what if c overlaps with a or b? The compiler must generate conservative scalar code unless instructed otherwise.

The Fix: __restrict__ and Memory Alignment

void multiply_arrays_fast(const float* __restrict__ a,
                          const float* __restrict__ b,
                          float* __restrict__ c,
                          size_t n) {
    // Hint that n is a multiple of vector width
    for (size_t i = 0; i < n; ++i) {
        c[i] = a[i] * b[i];
    }
}

By adding __restrict__, you guarantee to the compiler that the pointer memory regions do not overlap. Adding #pragma GCC ivdep or std::assume_aligned<32>(ptr) allows the compiler to emit aligned load instructions (vmovaps) instead of slower unaligned loads (vmovups).

Level 2: Explicit AVX2 Intrinsics

When algorithms have complex conditional branching or non-trivial stride patterns, compilers fail to auto-vectorize. This is where intrinsics (<immintrin.h>) give you direct access to machine instructions without writing assembly.

Let’s compute the Dot Product of two large vectors of 32-bit floats using AVX2 and FMA (Fused Multiply-Add):

#include <immintrin.h>
#include <cstddef>
#include <iostream>
#include <vector>

float dot_product_avx2(const float* a, const float* b, size_t n) {
    // 256-bit accumulator initialized to zeroes
    __m256 sum = _mm256_setzero_ps();

    size_t i = 0;
    // Process 8 floats per iteration
    for (; i + 7 < n; i += 8) {
        // Load 8 floats from memory
        __m256 va = _mm256_loadu_ps(a + i);
        __m256 vb = _mm256_loadu_ps(b + i);

        // Fused Multiply-Add: sum = (va * vb) + sum
        sum = _mm256_fmadd_ps(va, vb, sum);
    }

    // Horizontal sum of the 8 lanes in the vector register
    // sum = [s7, s6, s5, s4, s3, s2, s1, s0]
    __m128 lo = _mm256_castps256_ps128(sum);
    __m128 hi = _mm256_extractf128_ps(sum, 1);
    __m128 sum128 = _mm_add_ps(lo, hi); // [s7+s3, s6+s2, s5+s1, s4+s0]

    sum128 = _mm_hadd_ps(sum128, sum128);
    sum128 = _mm_hadd_ps(sum128, sum128);

    float result = _mm_cvtss_f32(sum128);

    // Clean up remaining tail elements
    for (; i < n; ++i) {
        result += a[i] * b[i];
    }

    return result;
}

Benchmark Comparison: Dot Product (10,000,000 Elements)

Benchmarked on an Intel Core i7 / AMD Zen 4 processor with -O3 -mavx2 -mfma:

Implementation Execution Time Speedup Factor
Naive Scalar Loop 18.2 ms 1.0x (Baseline)
Auto-vectorized (-O3) 4.6 ms 3.9x
Hand-written AVX2 + FMA 2.4 ms 7.6x
4-way Unrolled AVX2 + FMA 1.9 ms 9.5x

Why Unrolling Maximizes FMA Pipeline Latency

Notice that 4-way unrolling yielded additional speedup. Modern CPUs feature two FMA execution units with a 4-cycle latency. By using 4 separate accumulator registers (sum0, sum1, sum2, sum3), we break the read-after-write dependency chain, saturating CPU execution ports completely.

Common SIMD Pitfalls to Avoid

  1. Unaligned Memory Access: Reading unaligned memory across cache line boundaries causes cache line splits, incurring a penalty. Allocate vectors with posix_memalign, _aligned_malloc, or C++17 std::aligned_alloc(32, size).
  2. Branching Inside Vector Loops: Avoid if/else inside vector loops. Use blend and mask instructions (_mm256_blendv_ps, _mm256_cmp_ps) to compute both paths and select elements conditionally without CPU branch mispredictions.
  3. CPU Frequency Throttling: On older Intel architectures (Skylake/Haswell), heavy AVX-512 code caused the core to throttle down its clock speed. On modern AMD Zen 4/5 and Intel Raptor Lake / Arrow Lake, frequency downclocking is negligible.

Mastering SIMD elevates your code from ordinary C++ performance to hardware-saturating speeds.

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